1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to semiconductor integrated circuit devices comprising internal reset circuits for resetting predetermined internal circuits when a power supply is turned on.
2. Description of the Background Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an EPROM (Erasable and Programmable Read Only Memory), includes an internal circuit which should be reset at a start of an operation. Such resetting comprises initialization of an internal register or initialization of controlling redundancy circuit. For this purpose, the circuit provided in the device is an internal reset circuit. The internal reset circuit generates a one shot pulse when an external power supply which drives the semiconductor memory device is turned on and applies the same to a predetermined internal circuit, thereby carrying out "initialization" for the predetermined internal circuit.
FIG. 9 is a schematic block diagram of a dual port memory, one of the semiconductor integrated circuit devices having internal reset circuits. The dual port memory comprises a random accessible memory cell array having memory cells arranged in matrix and a serially accessible data register, which memory is for use as a frame memory of a video recorder, for example.
In FIG. 9, a memory cell array 101 comprises 4 submemory cell arrays each including a plurality (=512.times.512) of memory cells arranged in 512 rows and in 512 columns. An address buffer 102 externally receives address signals A0-A8. A row decoder 103 receives the address signals from address buffer 102 to select one row of memory cell array 101. A column decoder 104 receives the address signals from address buffer 102 to select one column of memory cell array 101. The data in the memory cells selected by row decoder 103 and column decoder 104 is outputted to a data input/output terminal r through a sense amplifier.multidot.I/O control circuit 105 and an I/O buffer 106. The four-bit data WIO.sub.0 -WIO.sub.3 applied to data input/output terminal r is inputted to the memory cells selected by row decoder 103 and column decoder 104 through I/O buffer 106 and sense amplifier.multidot.I/O control circuit 105, in each of 4 sub-memory cell arrays.
Meanwhile, a data register 107 comprises a plurality of registers arranged in one row. Data register 107 and memory cell array 101 transfer data to be written in or read from memory cells arranged in one row in the memory cell array 101 therebetween. An address pointer 108 sets the address signals applied from address buffer 102 for the address data to be applied to a serial data selector 109. The serial data selector 109 receives the address data set by the address pointer 108 to select 512 registers in data register 107. Serial data selector 109 includes a shift register sequentially selecting 512 registers in data register 107 or a decoder selecting 512 registers in data register 107 in response to the address signals. A serial I/O buffer 110 transfers serial input/output data SIO.sub.0 -SIO.sub.3 between serial data selector 109 and a data input/output terminals. A timing generator 111 externally receives a row address strobe signal RAS, a column address strobe signal CAS, a write per bit/write enable signal WV/WE, a data transfer/output enable signal DT/OE, a serial control signal SC and a serial enable signal SE to generate various timing signals for controlling an operation of each part.
A color register 113 temporarily stored the data applied to data input/output terminal r through I/O buffer 106 and applies the temporarily stored data to I/O buffer 106.
A write mask register 114 temporarily stores a mask bit instructing signal included in the data applied to data input/output terminal r through I/O buffer 106 and also applies the temporarily stored mask bit instructing signal to I/O buffer 106. The mask bit instructing signal instructs whether or not the data applied to data input/output terminal r is written in the memory cell.
At the start of the operation of the dual port memory, the above-described color register 113 and write mask register 114 should hold no data. Therefore, color register 113 and write mask register 114 need to be reset at the application of the external power supply (subsequently referred to as "power on"). Thus, the dual port memory includes a POR (Power-On-Reset Signal) generating circuit 112b which is an internal reset circuit.
POR generating circuit 112b outputs a one shot pulse POR to reset color register 113 and write mask register 114 at the power on.
FIG. 10 is a circuit diagram showing a common arrangement of such an internal reset circuit as described above.
Referring to FIG. 10, the internal reset circuit comprises series-connected capacitor C5 and N channel MOS transistor Q19 provided between a power supply Vcc and ground GND, a delay circuit 20, a latch circuit which is a reverse parallel circuit including inverters 22 and 23 provided between the node between capacitor C5 and transistor Q19 and delay circuit 20, and series-connected inverter 24 and delay circuit 21 provided between delay circuit 20 and the gate of the transistor Q19. An output .phi..sub.POR of the internal reset circuit is extracted from the output end of inverter 24.
The operation of the internal reset circuit will be described with reference to FIG. 11. FIG. 11 is a timing chart explaining the operation of the internal reset circuit.
When the power supply is turned on, the potential at the power supply Vcc rises as shown in FIG. 11(a). This potential rise is transmitted to the input end of inverter 22 through capacitor C5. As a result, a potential at a connection point (a node 16) between the input end of inverter 22 and 23 rises to a high level as shown in FIG. 11(b). Meanwhile, the potential at the output end of inverter 22 driven by the power supply Vcc starts rising upon the turning-on of the power supply as shown in FIG. 11(c). However, since the potential at the input end of inverter 22, that is, the potential at node 16 instantly attains a high level, the potential at the output end of inverter 22 instantly drops to a low level in response thereto. The potential level "L" (logical low) of the output end of inverter 22 is inverted by inverter 23 and applied to the input end of inverter 22. As a result, the potential level of node 16 is fixed to a "H", so that a logical "L" level is latched at a node 17 which is a connection point between the output end of inverter 22 and inverter 23.
The potential at node 17, after being delayed by delay circuit 20, is inputted to inverter 24. Therefore, the potential at node 17 appears at an input end 18 of inverter 24 with a the delay time .tau.1 in delay circuit 20, as shown in FIG; 11(d). Since inverter 24 inverts the output potential of delay circuit 20 to be outputted, the output potential of inverter 24, that is, the output .phi..sub.POR of the internal reset circuit rises to a high level upon the turning-on of the power supply as shown in FIG. 11 (e).
The output of inverter 24 is applied to the predetermined internal circuit and it is also delayed by delay circuit 21. The delayed output is applied to gate 19 of transistor Q19. The potential at gate 19 of transistor Q19 accordingly attains a high level later than the output potential of inverter 24 does with a delay time .tau.2 in delay circuit 21, as shown in FIG. 11 (f).
When the potential at gate 19 attains a high level, transistor Q19 conducts. As a result, the potential at node 16 drops from the high level to a low level in response to a low potential at ground GND. Namely, the potential at node 16, after once attaining a high level upon the turning-on of the power supply, is maintained at a high level for the period corresponding to the sum of the delay times .tau.1 and .tau.2 in delay circuits 20 and 21, respectively and then the potential attains a low level (see FIG. 11 (b)).
When the potential at node 16 attains the low level, the potential at node 17 rises from the low level to a high level by an inverting operation of inverter 22. This time, logical levels "L" and "H" are latched in nodes 16 and 17 by inverters 22 and 23, respectively. More specifically, the potential at node 17 attains a low level shortly after the slight rise upon the turning-on of the power supply and then it attains a high level in response to the potential at node 16 attaining a low level (see FIG. 11 (c)).
Meanwhile, the potential at node 17 is delayed by delay circuit 20 and then inverted by inverter 24, as described above. Therefore, the potential at input end 18 of inverter 24 rises later than the potential at node 17 does with the delay time .tau.1 after the turning-on of the power supply (see FIG. 11 (d)). The output .phi..sub.POR of inverter 24 rises to a high level upon the turning-on of the power supply and then after being maintained at a high level for a period corresponding to the delay time .tau.1 in delay circuit 20, the output drops to a low level (see FIG. 11 (e)).
The output potential of inverter 24 is fed back to gate 19 of transistor Q19 through delay circuit 21. As shown in FIG. 10 (f), the potential at gate 19 of transistor Q19 accordingly once attains a high level for a certain period upon the turning-on of the power supply, and then attains a low level. When the potential at gate 19 drops from a high level to the low level, the transistor Q19 being conductive until then again becomes non-conductive. However, the potential at node 16 is fixed to a low level hereinafter in response to the high level potential latched in node 17. As a result, after dropping from the high level to a low level upon the turning-off of the power supply, the potentials at node 16, gate 19 and the output end of inverter 24 are maintained at the low level. After rising from the low level to a high level upon the turning-on of the power supply. The potentials at node 17 and the input end 18 of inverter 24 are maintained at the high level.
As a result of such operations of the internal reset circuit as the foregoing, the signal attaining a high level for a certain period, that is, one shot pulse is inputted from inverter 24 upon a turning-on of the power supply. The one pulse is a power-on-reset signal POR for resetting the predetermined internal circuit.
As the foregoing, a conventional internal reset circuit provided in a semiconductor integrated circuit device is structured so as to output one shot pulse by utilizing a rise of a power supply voltage, thereby causing such problems as follows. These problems will be described with reference to FIGS. 12 and 13, taking the internal reset signal shown in FIG. 10 as an example. FIG. 12 is a circuit diagram showing in more detail the internal reset circuit shown in FIG. 10. FIG. 13 is a timing chart explaining the operations of the internal reset circuit of FIG. 10 when a power supply voltage is slow in rising after a power supply is turned on. Referring to FIG. 12, inverters 22, 23 and 24 comprise series-connected P channel MOS transistor Q26 and N channel MOS transistor Q27, series-connected P channel MOS transistor Q24 and N channel MOS transistor Q25 and series-connected P-channel MOS transistor Q28 and N channel MOS transistor Q29, respectively, each transistor being provided between a power supply Vcc and ground GND.
The previously described operations of the internal reset circuit shown in FIG. 10 correspond to a quick rise of the power supply voltage after the power supply is turned on. However, the rise rate of the power supply voltage after turning-on of the power supply varies depending on the capacitance of the semiconductor integrated circuit device to be driven by the applied power supply or the like.
For example, as shown in FIG. 13 (a), when the power supply voltage rises very slowly (for example taking more than 100 ms) after a turning-on of the power supply, the potential at node 16 receiving the power supply voltage through capacitor C5 in FIG. 12 also starts rising slowly as shown in FIG. 13 (b). Thus, the potential at node 16 does not rapidly rise to the level allowing transistor Q27 constituting inverter 22 to be rendered fully conductive. As a result, in inverter 22 after the turning-on of the power supply, transistor Q26 conducts for a long period. Therefore, the potential at the output end of inverter 22, that is, the potential at node 17 starts rising slowly in response to the potential at the power supply Vcc as shown in FIG. 13 (c). The potential at input end 18 of inverter 24 also slowly rises accordingly as shown in FIG. 13 (d). Namely, the potential at the input end 18 is maintained at a low potential allowing transistor Q28 constituting inverter 24 to conduct for a long period after the turning-on of the power supply. As a result, the output potential at inverter 24 and the potential at gate 19 of transistor Q19 also rise slowly as the rise of the power supply voltage as shown in FIGS. 13 (e) and (f), respectively.
When the potential at gate 19 of transistor Q19 reaches a threshold voltage of transistor Q19, transistor Q19 conducts to lower the potential at node 16 to the low potential of ground GND. Accordingly, while the potential at node 16 gradually rises after the turning-on of the power supply, it is pulled down to a low level before rising to a high level.
When the potential at node 16 is pulled down to the low level, transistor Q26 constituting inverter 22 becomes more fully conductive. In response thereto, the potential at node 17 rises to the then power supply voltage and thereafter, it rises at approximately the same rise rate as that of the power supply potential to duly attain a high level. The potential change of the node 17 appears at input end 18 of inverter 24 with the delay time .tau.1, whereby the potential at the input end 18 similarly changes to the potential at node 17. As a result, the potential at input end 18 reaches the threshold voltage of inverter 24, thereby pulling down the increasing output potential at inverter 24 to a low level. Consequently, the output potential of inverter 24 gradually rises after the turning-on of the power supply. However, the rising rate is so slow that the output potential is pulled down to a low level before rising to a high level. This output potential change of inverter 24 appears at gate 19 of transistor Q19 with the delay time .tau.2 in delay circuit 21. The potential at gate 19 of transistor Q 19 accordingly changes similarly to the output potential at inverter 24 does. Namely, while the potential at gate 19 rises to the threshold voltage of transistor Q19 after the turning-on of the power supply, it attains a low level shortly after that to render transistor Q19 non-conductive.
Since transistor Q25 is maintained in an on state in response to the high level potential latched in node 17 after transistor Q19 becomes non-conductive, the potentials at node 16, gate 19 and the output end of inverter 24 are maintained at a low level and the potentials at node 17 and input end 18 attain a high level in due course and it is fixed to the level.
As can be understood from the above, if the rise rate of the power supply voltage is slow, the output potential of inverter 24 is pulled down to a low level before rising to a high level after the turning-on of the power supply.
Therefore, the potential of the output (output .phi..sub.POR of this internal reset circuit) of inverter 24 takes the waveform as shown in FIG. 13 (e) not including the complete high level portion for a certain period after a turning-on of the power supply as shown in FIG. 11 (e).
Meanwhile, the internal circuit to be reset by the output signal of the internal reset circuit generating a high level one shot pulse is reset for a period when a high level signal is applied from the internal reset circuit as a result of a potential level at a predetermined node therein forced to a level to be obtained in an initial state. Thus, in order to fully reset the internal circuit, such one shot pulse should be generated as having a level and a width allowing the predetermined node to be fully forced to the level to be obtained in the initial state. Therefore, when the rise rate of the power supply potential after the turning-on of the power supply is slow, it sometimes occurs that a sufficient one shot pulse can not be obtained from the conventional internal reset circuit for resetting the internal circuit. Consequently, according to a conventional internal reset circuit, an internal circuit might not be fully reset depending on a rise rate of a power supply voltage to cause malfunction of the device.